In German Patent No. DE 44 16 881 A1, a data flow processor ("DFP") is described in which the lines of each edge cell (i.e., a cell at the edge of a cell array, often in direct contact with the terminals of the unit) are guided out via the terminals of the unit. The lines do not have any specific function, and instead they assume the function implemented in the edge cells. If several DFPs are interconnected, all terminals are connected to form a matrix.
In systems with two- or multi-dimensional programmable cell architectures (FPGAs, DPGAs), a certain subset of internal bus systems and lines of the edge cells are connected to the outside via the unit terminals. The lines do not have any specific function, and instead they assume the function written in the edge cells. If several FPGAs/DPGAs are interconnected, the terminals assume the function implemented in the hardware or software.
The wiring expense for the periphery or for interconnecting DFPs is very high, because the programmer must ensure that the respective functions are integrated into the cells of the DFP(s) at the same time. For connecting a memory, a memory management unit must be integrated into the unit. Connection of peripherals must also be supported. Additionally, the cascading of DFPs must be similarly taken into account. Not only is the expense relatively high, but also area on the unit is lost for the respective implementations. This also applies to FPGAs and DPGAS, particularly when they are used for implementation of algorithms and when they work as arithmetic (co)processors.